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fn6982 rev 1.00 page 1 of 21 november 19, 2009 fn6982 rev 1.00 november 19, 2009 qlx4300-s45 quad lane extender datasheet the qlx4300-s45 is a settable quad receive-side equalizer with extended functionality for advanced protocols operating with li ne rates up to 3.125gb/s such as infiniband (sdr) and 10gbase-cx4. the qlx4300-s45 compensates for the frequency dependent attenuation of copper twin-axial cables, extending the signal reach up to 40m on 24awg cable. the small form factor, highly-integrated quad design is ideal for high-density data transmission applications including active copper cable assemblies. the four equalizing filters within the qlx4300-s45 can each be set to one of 32 compensation levels, providing optimal signal fidelity for a given media and length. the compensation level for each filter can be set by either (a) three external control pins or (b) a serial bus interface. when the external control pins are used, 18 of the 32 boost levels are available for each channel. if the serial bus is used, all 32 compensation levels are available. operating on a single 1.2v power supply, the qlx4300-s45 enables per channel throughputs of up to 3.125gb/s while supporting the lower data rates of 2.5gb/s and 1.5gb/s. the qlx4300-s45 uses current mode logic (cml) inputs/outputs and is packaged in a 4mmx7mm 46 lead qfn. individual lane impedance select support is included for module applications. features ? supports data rates up to 3.125gb/s ? low power (78mw per channel) ? low latency (<500ps) ? four equalizers in a 4mmx7mm qfn package for straight route-through architecture and simplified routing ? each equalizer boost is independently pin selectable and programmable ? beacon signal support and line silence preservation ?1.2v supply voltage ? individual channel power-down (impedance select) applications ?infiniband (sdr) ?10gbase-cx4 ? pci express (gen 1) ?displayport ?xaui ? sas (1.0) ? high-speed active cable assemblies ? high-speed printed circuit board (pcb) traces benefits ? thinner gauge cable ? extends cable reach greater than 3x ?improved ber typical application circuit qlx4300-s45 qlx4300-s45 <40m 24awg
qlx4300-s45 fn6982 rev 1.00 page 2 of 21 november 19, 2009 pin configuration qlx4300-s45 (46 ld 4x7 qfn) top view ordering information part number (note) part marking temp. range (c) package (pb-free) pkg. dwg. # QLX4300SIQT7 qlx4300siq 0 to +70 46 ld qfn 7? prod. tape & reel; qty 1,000 l46.4x7 qlx4300siqsr qlx4300siq 0 to +70 46 ld qfn 7? sample reel; qty 100 l46.4x7 note: these intersil pb-free plastic packag ed products employ specia l pb-free material sets; molding compounds/die attach materials and nipdau plate - e4 termination finish, which is rohs compliant and compatible with both snpb and pb-free solderin g operations. intersil pb-free products are msl classified at pb- free peak reflow temper atures that meet or exceed the pb-free requirements of ipc/jedec j std-020. dt in1[p] in1[n] v dd in2[p] in2[n] v dd clk enb cp1[a] cp1[b] cp1[c] cp2[b] cp2[a] 1 2 3 4 5 6 7 46 45 44 43 42 41 40 8 9 10 11 12 13 14 15 39 16 17 18 19 20 21 22 23 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 in3[p] in3[n] v dd in4[p] in4[n] is1 is2 gnd bgref out1[p] out1[n] v dd out2[p] out2[n] v dd out3[p] out3[n] v dd out4[p] out4[n] is3 is4 mode cp2[c] exposed pad cp3[c] cp4[b] do cp3[a] di cp3[b] cp4[a] cp4[c] (gnd)
qlx4300-s45 fn6982 rev 1.00 page 3 of 21 november 19, 2009 pin descrptions pin name pin number description dt 1 detection threshold. referenc e dc current threshold for input signal power detection. data output out[k] is muted when the power of the equalized version of in[k] falls below the threshold. tie to ground to disa ble electrical idle preservation and always enable the limiting amplifier. in1[p,n] 2, 3 equalizer 1 differential input, cml. the use of 100nf low esl/esr mlcc capacitor with at least 4ghz frequency respon se is recommended. v dd 4, 7, 10, 29, 32, 35 power supply. 1.2v supply voltage. the use of pa rallel 100pf and 10nf decoupling capacitors to ground is recommended for each of these pins for broad high-frequen cy noise suppression. in2[p,n] 5, 6 equalizer 2 differential input, cml. the use of 100nf low esl/esr mlcc capacitor with at least 4ghz frequency respon se is recommended. in3[p,n] 8, 9 equalizer 3 differential input, cml. the use of 100nf low esl/esr mlcc capacitor with at least 4ghz frequency respon se is recommended. in4[p,n] 11, 12 equalizer 4 differential input, cml. the use of 100nf low esl/esr mlcc capacitor with at least 4ghz frequency respon se is recommended. is1 13 impedance select 1. cmos logic input. when the voltage on this pin is low, the single-ended input impedance of in1p and in1n each go above 200k ? and powers down th e channel. this pin should be connected to the fundamental reset signal in pci express?. otherwise, connect to v dd to hold the input impedance at 50 ? . is2 14 impedance select 2. cmos logic input. when the voltage on this pin is low, the single-ended input impedance of in2p and in2n each go above 200k ? and powers down th e channel. this pin should be connected to the fundamental reset signal in pci express?. otherwise, connect to v dd to hold the input impedance at 50 ? . gnd 15 ground di 16 serial data input, cmos logi c. input for serial data stream to program internal registers controlling the boost for all four equalizers. sync hronized with clock (clk) on pin 46. overrides the boost setting establis hed on cp control pins. internally pulled down. do 17 serial data output, cmos logic. output of the internal registers controlling the boost for all four equalizers. synchronized with clock on pin 46. equi valent to serial data input on di but delayed by 21 clock cycles. cp3[a,b,c] 18, 19, 20 control pins for setting equalizer 3. cm os logic inputs. pins are read as a 3-digit number to set the boost level. a is the msb, and c is the lsb. pins are internally pulled down through a 25k ? resistor. cp4[a,b,c] 21, 22, 23 control pins for setting equalizer 4. cm os logic inputs. pins are read as a 3-digit number to set the boost level. a is the msb, and c is the lsb. pins are internally pulled down through a 25k ? resistor. mode 24 boost-level control mode input, cmos logic. allows serial programming of internal registers through pins di, enb, and clk when set high. resets all internal registers to zero and uses boost levels set by cp pins when se t low. if serial programming is not used, this pin should be grounded. is4 25 impedance select 4. cmos logic input. when the voltage on this pin is low, the single-ended input impedance of in4p and in4n each go above 200k ? and powers down th e channel. this pin should be connected to the fundamental reset signal in pci express?. otherwise, connect to v dd to hold the input impedance at 50 ? . is3 26 impedance select 3. cmos logic input. when the voltage on this pin is low, the single-ended input impedance of in3p and in3n each go above 200k ? and powers down th e channel. this pin should be connected to the fundamental reset signal in pci express?. otherwise, connect to v dd to hold the input impedance at 50 ? . out4[n,p] 27, 28 equalizer 4 differentia l output, cml. the use of 100nf low esl/esr mlcc capacitor with at least 4ghz frequency respon se is recommended. out3[n,p] 30, 31 equalizer 3 differentia l output, cml. the use of 100nf low esl/esr mlcc capacitor with at least 4ghz frequency respon se is recommended.
qlx4300-s45 fn6982 rev 1.00 page 4 of 21 november 19, 2009 out2[n,p] 33, 34 equalizer 2 differentia l output, cml. the use of 100nf low esl/esr mlcc capacitor with at least 4ghz frequency respon se is recommended. out1[n,p] 36, 37 equalizer 1 differentia l output, cml. the use of 100nf low esl/esr mlcc capacitor with at least 4ghz frequency respon se is recommended. bgref 38 external bandgap reference re sistor. recommended value of 6.04k ? 1%. cp2[c,b,a] 39, 40, 41 control pins for setting equalizer 2. cm os logic inputs. pins are read as a 3-digit number to set the boost level. a is the msb, and c is the lsb. pins are internally pulled down through a 25k ? resistor. cp1[c,b,a] 42, 43, 44 control pins for setting equalizer 1. cm os logic inputs. pins are read as a 3-digit number to set the boost level. a is the msb, and c is the lsb. pins are internally pulled down through a 25k ? resistor. enb 45 serial data enable (active low), cmos logic. internal register s can be programmed with di and clk pins only when the enb pin is ?low?. internally pulled down. clk 46 serial data clock, cmos logic. synchronous clock for serial data on di and do pins. data on di is latched on the rising cloc k edge. clock speed is recommen ded to be between 10mhz and 20mhz. internally pulled down. exposed pad - exposed ground pad. for proper electrical and thermal performance, this pad should be connected to the pcb ground plane. pin descrptions (continued) pin name pin number description
qlx4300-s45 fn6982 rev 1.00 page 5 of 21 november 19, 2009 absolute maximum ratings thermal information supply voltage (v dd to gnd) . . . . . . . . . . . . -0.3v to 1.3v voltage at all input pins . . . . . . . . . . . -0.3v to v dd + 0.3v esd rating at all pins . . . . . . . . . . . . . . . . . . . . 2kv (hbm) thermal resistance (typical) ? ja (c/w) ? jc (c/w) 46 ld qfn package (note 1). . . . . 32 2.3 operating ambient temperature range. . . . . . 0c to +70c storage ambient temperature range . . . . . -55c to +150c maximum junction temperature. . . . . . . . . . . . . . . +125c pb-free reflow profile. . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. note: 1. ? ja is measured with the component mounted on a high effective thermal conductivity test board in free air. see tech brief tb379 for details. operating conditions parameter symbol condition min typ max units supply voltage v dd 1.1 1.2 1.3 v operating ambient temperature t a 02570c bit rate nrz data applied to any channel 1.5 3.125 gb/s control pin characteristics typical values are at v dd = 1.2v, t a = +25c, and v in = 800mv p-p , unless otherwise noted. v dd = 1.1v to 1.3v, t a = 0c to +70c. parameter symbol condition min typ max units notes input ?low? logic level v il di, clk, enb 0 0 350 mv input ?high? logic level v ih di, clk, enb 750 v dd mv output ?low? logic level v ol is[k], do 0 0 250 mv output ?high? logic level v oh is[k], do 1000 v dd mv ?low? resistance state cp[k][a,b,c] 0 1 k ? 2 ?mid? resistance state cp[k][b,c] 22.5 25 27.5 k ? 2 ?high? resistance state cp[k][a,b,c] 500 ? k ? 2 input current current draw on digital pin, i.e., cp[k][a,b,c], di, clk, enb 30 100 a note: 2. if four cp pins are tied together, the resistance values in this table sh ould be divided by four. electrical specifications typical values are at v dd = 1.2v, t a = +25c, and v in = 800mv p-p , unless otherwise noted. v dd = 1.1v to 1.3v, t a = 0c to +70c. parameters symbol condition min typ max units notes supply current i dd 260 ma cable input amplitude range v in measured differentially at data source before encountering channel loss 800 1200 1600 mv p-p 3 dc differential input resistance measured on input channel in[k] 80 100 120 ? dc single-ended input resistance measured on input channel in[k]p or in[k]n 40 50 60 ? input return loss (differential) s dd 11 50mhz to 3.75ghz 10 db 4 input return loss (common mode) s cc 11 50mhz to 3.75ghz 6 db 4
qlx4300-s45 fn6982 rev 1.00 page 6 of 21 november 19, 2009 input return loss (com. to diff. conversion) s dc 11 50mhz to 3.75ghz 20 db 4 output amplitude range v out active data transmission mode; measured differentially at out[ k]p and out[k]n with 50 ? load on both output pins 450 550 650 mv p-p line silence mode; measured differentially at out[k]p and out[k]n with 50 ? load on both output pins 10 20 mv p-p differential output impedance measured on out[k] 80 105 120 ? output return loss (differential) s dd 22 50mhz to 3.75ghz 10 db 4 output return loss (common mode) s cc 22 50mhz to 3.75ghz 5 db 4 output return loss (com. to diff. conversion) s dc 22 50mhz to 3.75ghz 20 db 4 output residual jitter 3.125gb/ s; up to 20m 24awg standard twin-axial cable (approx. -25db @ 2.5ghz); 800mv p-p ?? v in ? 1600mv p-p 0.15 0.25 ui 3, 5, 6 output transition time t r , t f 20% to 80% 306080 ps 7 lane-to-lane skew 50 ps propagation delay from in[k] to out[k] 500 ps data-to-line silence response time t ds time to transition from active data to line silence (muted output) on 20m 24awg standard twin-axial cable at 3.125gb/s 15 ns 8, 11 time from last bit of align(0) for sas oob signaling to line silence (<20mv p-p output); meritec 24awg 20m; 3.125gb/s 14 ns 12 line silence-to-data response time t sd time to transition fro m line silence mode (muted output) to active data on 20m 24awg standard twin-axial cable at 3.125gb/s 20 ns 8, 11 time from first bit of align(0) for sas oob signaling to 450mv p-p output; meritec 24awg 20m; 3.125gb/s 19 ns 12 timing difference (sas) |t ds - t sd | for sas oob signal ing support; meritec 24awg 20m 5ns12 notes: 3. after channel loss, differential amplitudes at qlx4300-s45 inpu ts must meet the input voltage range specified in ?absolute maximum ratings? on page 5. 4. temperature = +25c, v dd = 1.2v. 5. output residual jitter is the difference between the total jitter at the lane extender output and the total jitter of the tra nsmitted signal (as measured at the input to the channel). total jitter (tj) is dj pp + 14.1 x rj rms . 6. measured using a prbs 2 7 -1 pattern. deterministic jitter at the input to the lane extender is due to frequency-dependent, media-induced loss only. 7. rise and fall times measured using a 1ghz clock with a 20ps edge rate. 8. for active data mode, cable input amplitude is 400mv p-p (differential) or greater. for line silence mode, cable input amplitude is 20mv p-p (differential) or less. 9. measured differentially across the data source. electrical specifications typical values are at v dd = 1.2v, t a = +25c, and v in = 800mv p-p , unless otherwise noted. v dd = 1.1v to 1.3v, t a = 0c to +70c. (continued) parameters symbol condition min typ max units notes
qlx4300-s45 fn6982 rev 1.00 page 7 of 21 november 19, 2009 notes: (continued) 10. during line silence, transmitter noise in excess of this voltage range may result in differential output amplitudes from the qlx4300-s45 that are greater than 20mv p-p . 11. the data pattern preceding line silence mo de is comprised of the pcie electrical idle ordered set (eios). the data pattern following line silence mode is comprised of the pcie electrical idle exit sequence (eies). 12. the data pattern preceding or following line silence mode is comprised of the sas-2 align (0) sequence for oob signaling at 3.125gb/s, and amplitude of 800mv p-p . serial bus timing characteristics parameter symbol condition min typ max units clk setup time t sck from the falling edge of enb 10 ns di setup time t sdi prior to the rising edge of clk 10 ns di hold time t hdi from the rising edge of clk 6 ns enb ?high? t hen from the falling edge of the last data bit?s clk 10 ns boost setting operational t d from enb ?high? 10 ns do hold time t cq from the rising edge of clk to do transition 12 ns clock rate f clk reference clock for serial bus eq programming 20 mhz typical performance characteristics v dd = 1.2v, t a = +25c, unless otherwise noted. performance was characterized using the system testbed shown in figure 1. unless otherwise noted, the transmitter generated a non-return-to-ze ro (nrz) prbs-7 sequence at 800mv p-p (differential) with 10ps of peak-to-peak deterministic jitter. this transmit signal was launched into twin-axial cable test channels of varying gauges and lengths. the loss characterist ics of these test channels are plotted as a function of frequency in figure 2. the received signal at the output of these test channels was then processed by the qlx4300-s45 before being passed to a receiver. eye diagram measurements were made with 4000 waveform acquisitions and include random jitter. figure 1. device characterization test setup figure 2. 26 awg twin-axial cable loss as a fu nction of frequency for various test channels pattern generator sma adapter card 100o twin-axial cable sma adapter card qlx4300-s45 eval board oscilloscope ? -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 0123456 frequency (ghz) sdd21 (db) 10m 15m 20m 25m
qlx4300-s45 fn6982 rev 1.00 page 8 of 21 november 19, 2009 figure 2. jitter vs boost setting for various cable lengths, prbs-7, 0.03ps system jitter included output eye diagrams figure 3. received signal after 10m of 26awg twin-axial cable, 3.125gb/s figure 4. qlx4300-s45 output after 10m of 26awg twin-axial cable, 3.125gb/s figure 5. received signal after 15m of 26awg twin-axial cable, 3.125gb/s figure 6. qlx4300-s45 output after 15m of 26awg twin-axial cable, 3.125gb/s typical performance characteristics (continued) 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0 5 10 15 20 25 30 35 boost setting jitter (ps) 10m 15m 20m 25m
qlx4300-s45 fn6982 rev 1.00 page 9 of 21 november 19, 2009 figure 7. received signal after 20m of 26awg twin-axial cable, 3.125gb/s figure 8. qlx4300-s45 output after 20m of 26awg twin-axial cable, 3.125gb/s figure 9. received signal after 25m of 26awg twin-axial cable, 3.125gb/s figure 10. qlx4300-s45 output after 25m of 26awg twin-axial cable, 3.125gb/s return loss and cro sstalk characteristics figure 11. input common-mode return loss figure 12. output common-mode return loss typical performance characteristics (continued) 64ps/div 70mv/div 64ps/div 80mv/div 64ps/div 60mv/div 64ps/div 60mv/div -30 -25 -20 -15 -10 -5 0 00.511.522.533.54 frequency (ghz) scc11 (db) channel 1 channel 2 channel 3 channel 4 -30 -25 -20 -15 -10 -5 0 0 0.5 1 1.5 2 2.5 3 3.5 4 frequency (ghz) scc22 (db) channel 1 channel 2 channel 3 channel 4
qlx4300-s45 fn6982 rev 1.00 page 10 of 21 november 19, 2009 operation the qlx4300-s45 is an advanced quad lane-extender for high-speed interconnects. a f unctional diagram of one of the four channels in th e qlx4300-s45 is shown in figure 17. in addition to a robust equalization filter to compensate for channel loss and restore signal fidelity, the qlx4300-s45 contains unique integrated features to preserve special signaling pr otocols typically broken by other equalizers. the signal detect function is used to mute the channel output when the equalized signal falls below the level determined by the detection threshold (dt) pin voltage. this function is intended to preserve periods of line silence (?quiescent state? in infiniband contexts). as illustrated in figure 17, the core of each high-speed signal path in the qlx4300-s45 is a sophisticated equalizer followed by a limiting amplifier. the equalizer compensates for skin loss, dielectric loss, and impedance discontinuities in the transmission channel. each equalizer is followed by a lim iting amplification stage that provides a clean output signal with full amplitude swing and fast rise-fall times for reliable signal decoding in a subsequent receiver. individually adjustab le equalization boost each channel in the qlx4300-s45 features an independently settable equalizer for custom signal restoration. each equalizer can be set to one of 32 levels of compensation when the serial bus is used to program figure 13. input differential return loss figure 14. output differential return loss figure 15. differential crosstalk between adjacent input channel figure 16. differential crosstalk between adjacent input channels typical performance characteristics (continued) -35 -30 -25 -20 -15 -10 -5 0 00.511.522.533.54 frequency (ghz) sdd11 (db) channel 1 channel 2 channel 3 channel 4 -35 -30 -25 -20 -15 -10 -5 0 00.511.522.533.54 frequency (ghz) sdd22 (db) channel 1 channel 2 channel 3 channel 4 + - settable equilizer limiting amplifier amplitude detector mute enabled out[k] in[k] is[k] >200k ? bit select (cp[k]/di) dt
qlx4300-s45 fn6982 rev 1.00 page 11 of 21 november 19, 2009 the boost level and one of 18 compensation levels when the cp[k] pins are used to set the level. the equalizer transfer functions for a subset of these compensation levels are plotted in figure 18. the flexibility of this adjustable compensation architecture enables signal fidelity to be optimized on a channel-by-channel basis, providing support for a wide variety of channel characteristics and data rates ranging from 2.5gb/s to 3.125gb/s. because the boost level is externally set rather than internally adapted, the qlx4300-s45 provides reliable communication from the very first bit transmitted. there is no time needed for adaptation and control loop convergence. furthermore, there are no pathological data patterns that will cause the qlx4300-s45 to move to an incorrect boost level. the ?applications information? section beginning on page 12 details how to set the boost level by both the cp-pin voltage approach and the serial programming approach. cml input and ou tput buffers the input and output buffers for the high-speed data channels in the qlx4300-s45 are implemented using cml. equivalent input and output circuits are shown in figures 19 and 20, respectively. line silence/electrical idle/quiescent mode line silence is commonly broken by the limiting amplification in other equalizers. this disruption can be detrimental in many systems that rely on line silence as part of the protocol. the qlx4300-s45 contains special lane management capabilities to detect and preserve periods of line silence while still providing the fidelity-enhancing benefits of limiting amplification during active data transmission. line silence is detected by measuring the amplitude of the equalized signal and comparing that to a threshold set by the current at the dt pin. when the amplitude falls below the threshold, the output driver stages are muted and held at their nominal common mode voltage 1 . figure 18. equalizer transfer functions for settings 0, 5, 10, 15, 20, 25, and 31 in the qlx4300-s45 figure 19. cml input equivalent circuit for the qlx4300-s45 figure 20. cml output equivalent circuit for the qlx4300-s45 note: the load value of 52 ? is used to internally match sdd 22 for a characterist ic impedance of 50 ? . 1. the output common mode voltage remains constant during both a ctive data transmission and output muting modes. in[k] p in[k] n buffer v dd 50 50 v dd 52 52 out[k] p out[k] n
qlx4300-s45 fn6982 rev 1.00 page 12 of 21 november 19, 2009 channel power-down in addition to controlling the input impedance, the is[k] pin powers down the equalizer channel when pulled low. this feature allows a system controller individually to power down unused channels and to minimize power consumption. example: the signal to power down a channel could come from an intelligent platform management controller in atca applications for e-keying. the current draw for a channel is reduced from 50ma to 3.8ma when powered down. applications information several aspects of the qlx4300-s45 are capable of being dynamically managed by a system controller to provide maximum flexibility and optimum performance. these functions are controlled by interfacing to the highlighted pins in figure 21. the specific procedures for controlling these aspects of the qlx4300-s45 are the focus of this section. figure 21. pin diagram highlighting pins used for dynamic control of the qlx4300-s45 dt in1[p] in1[n] v dd in2[p] in2[n] v dd clk enb cp1[a] cp1[b] cp1[c] cp2[b] cp2[a] 1 2 3 4 5 6 7 46 45 44 43 42 41 40 8 9 10 11 12 13 14 15 39 16 17 18 19 20 21 22 23 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 in3[p] in3[n] v dd in4[p] in43[n] is1 is2 gnd bgref out1[p] out1[n] v dd out2[p] out2[n] v dd out3[p] out3[n] v dd out4[p] out4[n] is3 is4 mode cp2[c] exposed pad cp3[c] cp4[b] do cp3[a] di cp3[b] cp4[a] cp4[c] (gnd) table 1. descriptions of pins that can be used to set equalization boost level pin name pin number description di 16 serial data input, cmos logic. input for serial data stream to program internal registers controlling the boost for all four equalizers. synchronized with clock (clk) on pin 46. overrides the boost setting established on cp contro l pins. internally pulled down. do 17 serial data output, cmos logic. output of the internal registers controlling the boost for all four equalizers. synchronized with clock on pin 46. equiva lent to serial data input on di but delayed by 21 clock cycles. cp3[a,b,c] 18, 19, 20 control pins for settin g equalizer 3. cmos logic inputs. pins ar e read as a 3-digit number to set the boost level. a is the msb, and c is the lsb. pins are internally pulled down through a 25k ? resistor. cp4[a,b,c] 21, 22, 23 control pins for settin g equalizer 4. cmos logic inputs. pins ar e read as a 3-digit number to set the boost level. a is the msb, and c is the lsb. pins are internally pulled down through a 25k ? resistor. mode 24 boost-level control mode input, cmos logic. allows serial programming of internal registers through pins di, enb, and clk when set ?high?. rese ts all internal registers to zero and uses boost levels set by cp pins when set lo w. if serial programming is not us ed, this pin should be grounded. cp2[c,b,a] 39, 40, 41 control pins for settin g equalizer 2. cmos logic inputs. pins ar e read as a 3-digit number to set the boost level. a is the msb, and c is the lsb. pins are internally pulled down through a 25k ? resistor. cp1[c,b,a] 42, 43, 44 control pins for settin g equalizer 1. cmos logic inputs. pins ar e read as a 3-digit number to set the boost level. a is the msb, and c is the lsb. pins are internally pulled down through a 25k ? resistor. enb 45 serial data enable (active low), cmos logic. in ternal registers can be programmed with di and clk pins only when the enb pin is ?low?. internally pulled down. clk 46 serial data clock, cmos logic. synchronous clock for serial data on di and do pins. data on di is latched on the rising clock e dge. clock speed is recommended to be between 10mhz and 20mhz. internally pulled down.
qlx4300-s45 fn6982 rev 1.00 page 13 of 21 november 19, 2009 equalization boost level channel equalization for the qlx4300-s45 can be individually set to either (a) one of 18 levels through the dc voltages on external control pins or (b) one of 32 levels via a set of registers programmed by a low speed serial bus. the pins used to control the boost level are highlighted in figure 21. descriptions of these pins are listed in table 1. please refer to ?pin descrptions? on page 3 for descriptions of all other pins on the qlx4300-s45. the boost setting for equalizer channel k can be read as a three digit ternary number across cp[k][a,b,c]. the ternary value is established by the value of the resistor between vdd and the cp[k][a,b,c] pin. as a second option, the equalizer boost setting can be taken from a set of registers programmed through a serial bus interface (pins 16, 17, 45, and 46). using this interface, a set of registers is programmed to store the boost level. a total of 21 registers are used. registers 2 through 21 are parsed into four 5-bit words. each 5-bit word determines which of 32 boost levels to use for the corresponding equalizer. register 1 instructs the qlx4300-s45 to use registers 2 through 21 to set the boost level rather than the control pins cp[k][a,b,c]. both options have their relative advantages. the control pin option minimizes the need for external controllers as the boost level can be set in the board design resulting in a compact layout. the register option is more flexible for cases in which the optimum boost level will not be known and can be changed by a host bus adapter with a small number of pins. it is noted that the serial bus interface can also be daisy-chained among multiple qlx4300-s45 devices to afford a compact programmable solution even when a large number of data lines need to be equalized. upon power-up, the default value of all the registers (and register 1 in particular) is zero, and thus, the cp pins are used to set the boost level. this permits an alternate interpretation on setting the boost level. specifically, the cp pins define the default boost level until the registers are (if ever) programmed via the serial bus. control pin boost setting when register 1 of the qlx4300-s45 is zero (the default state on power-up), the voltages at the cp pins are used to determine the boost level of each channel. for each of the four channels, k, the [a], [b], and [c] control pins (cp[k]) are associated with a 3-bit non binary word. while [a] can take one of two values, ?low? or ?high?, [b] and [c] can take one of three different values: ?low?, ?middle?, or ?high?. this is achieved by changing the value of a resistor connected between v dd and the cp pin, which is internally pulled low with a 25k ? resistor. thus, a ?high? state is achieved by using a 0 ? resistor, ?middle? is achieved with a 25k ? resistor, and ?low? is achieved with an open resistance. table 2 defines the mapping from the 3-bit cp word to the 18 out of 32 possible levels available via the serial interface. if all four channels are to use the same boost level, then a minimum number of board resistors can be realized by tying together like cp[k][a,b,c] pins across all channels k. for instance, all four cp[k][a] pins can be tied to the same resistor running to v dd . consequently, only three resistors are needed to control the boost of all four channels. if the cp pins are tied together and the 25k ? is used, the value changes to a 6.25k ? resistor because the 25k ? is divided by 4. table 2. mapping between cp-setting resistor and programmed boost levels resistance between cp pin and v dd serial boost level cp[a] cp[b] cp[c] open open open 0 open open 25k ? 2 open open 0 ? 4 open 25k ? open 6 open 25k ? 25k ? 8 open 25k ? 0 ? 10 open 0 ? open 12 open 0 ? 25k ? 14 open 0 ? 0 ? 15 0 ? open open 16 0 ? open 25k ? 17 0 ? open 0 ? 19 0 ? 25k ? open 21 0 ? 25k ? 25k ? 23 0 ? 25k ? 0 ? 24 0 ? 0 ? open 26 0 ? 0 ? 25k ? 28 0 ? 0 ? 0 ? 31
qlx4300-s45 fn6982 rev 1.00 page 14 of 21 november 19, 2009 optimal cable boost settings the settable equalizing filter within the qlx4300-s45 enables the device to optimally compensate for frequency-dependent attenuation across a wide variety of channels, data rates, and encoding schemes. for the reference channels plotted in figure 2, table 3 shows the optimal boost setting when transmitting a prbs-7 signal. the optimal boost setting is defined as the equalizing filter setting that minimizes the output residual jitter of the qlx4300-s45. the settings in table 4 represent the optimal settings for the qlx4300-s45 across an ambient temperature range of 0c to +70c. the optimal setting at room temperature (+20c to +40c) is generally one to two settings lower than the values listed in table 3. register description the qlx4300-s45?s internal registers are listed in table 4. register 1 determines whether the cp pins or register values 2 through 21 are used to set the boost level. when this register is set, the qlx4300-s45 uses registers 2-6, 7-11, 12-16, and 17-21 to set the boost level of equalizers 1, 2, 3, and 4. when register 1 is not set, the cp pins are used to determine the boost level for each equalizer channel. the use of five registers for each equalizer channel allows all 32 boost levels as candidate boost levels. table 3. optimal cable boost settings cable approx. loss @ 1.5625ghz (db) qlx4300-s45 boost cable a 17 12 cable b 23 16 cable c 28 23 note: optimal boost settings sh ould be determined on an application-by-applicat ion basis to account for variations in channel type, loss characteristics, and encoding schemes. the settings in this table are presente d as guidelines to be used as a starting point for application-specific optimization. table 4. description of in ternal serial registers register equalizer channel description 1 1-4 cp control override ? use registers 2 through 21 (rather than cp pins) to establish the boost levels when this bit is set. 2 1 equalizer setting bit 0 (lsb). 3 equalizer setting bit 1. 4 equalizer setting bit 2. 5 equalizer setting bit 3. 6 equalizer setting bit 4 (msb). 7 2 equalizer setting bit 0 (lsb). 8 equalizer setting bit 1. 9 equalizer setting bit 2. 10 equalizer setting bit 3. 11 equalizer setting bit 4 (msb). 12 3 equalizer setting bit 0 (lsb). 13 equalizer setting bit 1. 14 equalizer setting bit 2. 15 equalizer setting bit 3. 16 equalizer setting bit 4 (msb). 17 4 equalizer setting bit 0 (lsb). 18 equalizer setting bit 1. 19 equalizer setting bit 2. 20 equalizer setting bit 3. 21 equalizer setting bit 4 (msb).
qlx4300-s45 fn6982 rev 1.00 page 15 of 21 november 19, 2009 serial bus programming pins 16 (di), 45 (enb), and 46 (clk) are used to program the registers inside the qlx4300-s45. figure 22 shows an exemplary timing diagram for the signals on these pins. the serial bus can be used to program a single qlx4300-s45 according to the following steps: 1. the enb pin is pulled ?low?. - while this pin is ?low?, the data input on di are read into registers but not yet latched. - a setup time of t sck is needed between enb going ?low? and the first rising clock edge. 2. at least 21 values are read from di on the rising edge of the clk signal. - if more than 21 values are passed in, then only the last 21 values are kept in a fifo fashion. - the data on di should start by sending the value destined for register 21 and finish by sending the value destined for register 1. - a range of clock frequenc ies can be used. a typical rate is 10mhz. the clock should not exceed 20mhz. -setup (t sdi ) and hold (t hdi ) times are needed around the rising clock edge. 3. the enb pin is pulled ?high? and the contents of the registers are latched and take effect. - after clocking in the last data bit, an additional t hen should elapse before pulling the enb signal ?high?. - after completing these steps, the new values will affect within t d . programming multiple qlx4300-s45 devices the serial bus interface provides a simple means of setting the equalizer boost levels with a minimal amount of board circuitry. many of the serial interface signals can be shared among the qlx4300-s45 devices on a board and two options are presented in this section. the first uses common clock and serial data signals along with separate enb signals to select which qlx4300-s45 accepts the programmed changes. the second method uses a common enb signal as the serial data is carried-over from one qlx4300-s45 to the next. separate enb signals multiple qlx4300-s45 devices can be programmed from a common serial data stream as shown in figure 23. here, each qlx4300-s45 is provided its own enb signal, and only one of these enb signals is pulled ?low?, and hence accepting the register data one at a time. in this situation, the programming of each equalizer follows the steps outlined in figure 22. di/do carryover the do pin (pin 17) can be used to daisy-chain the serial bus among multiple qlx4300-s45 chips. the do pin outputs the overflow data from the di pin. specifically, as data is pipelined into a qlx4300-s45, it proceeds according to the following flow. first, a bit goes into shadow register 1. then, with each clock cycle, it shifts over into subsequent higher numbered registers. after shifting into register 21, it is output on the do pin on the same clock cycle. thus, the do signal is equal to the di signal, but delayed by 20 clock cycles. the timing diagram for the do pin is shown in figure 24 where the first 20 bits output from the do are indefinite and subsequent bits are the data fed into the di pin. the delay between the rising clock edge and the data transition is t cq . a diagram for programming mu ltiple qlx4300-s45s is shown in figure 25. it is noted that the board layout should ensure that the additional clock delay experienced between subsequent qlx4300-s45s should be no more than the minimum value of t cq , i.e. 12ns. figure 22. timing diagram for programming th e internal registers of the qlx4300-s45 r21 r20 r19 r1 t sdi t hdi t sck t hen di clk enb
qlx4300-s45 fn6982 rev 1.00 page 16 of 21 november 19, 2009 figure 23. serial bus programming multiple qlx4300-s45 devices using separate enb signals 4/[6 $ (1% &/. ', '2 4/[6 % (1% &/. ', '2 4/[6 & (1% &/. ', '2 4/[6 ' (1% &/. ', '2 (1%$ (1%% (1%& (1%' &orfn 6huldo 5hjlvwhu 'dwd figure 24. timing diagram for di/do carryover t sck do clk enb 20 clock cycles t cq 21 st rising edge first bit from di figure 25. serial bus programming multiple qlx4300-s45 devices using di/do carryover 4/[6 $ (1% &/. ', '2 4/[6 % (1% &/. ', '2 4/[6 & (1% &/. ', '2 4/[6 ' (1% &/. ', '2 (1% &orfn 6huldo 5hjlvwhu 'dwd
qlx4300-s45 fn6982 rev 1.00 page 17 of 21 november 19, 2009 detection thereshold (dt) pin functionality the qlx4300-s45 is capable of maintaining periods of line silence on any of its four channels by monitoring each channel for loss of signal (los) conditions and subsequently muting the outputs of a respective channel when such a condition is detected. a reference current applied to the detection threshold (dt) pin is used to set the los threshold of the internal signal detection circuitry. current control on the dt pin is done via one or two external resistors. nominally, both a pull-up and pull-down resistor are tied to the dt pin (figure 27a), but if adequate control of the supply voltage is maintained to within 3% of 1.2v, then a simple pull down resistor is adequate (as in figure 27b). resistors used should be at least 1/16w, with 1% precision. the internal bias point of the dt pin, nominally 1.05v, is used in conjunction with the voltage divider (r1 and r2) shown in figure 27a to set the reference current on the dt pin. case 1: channels with less than or equal to 17db loss at 1.5625ghz: for signals transmitted on channels having less than or equal to 25db of loss at 2.5ghz, the optimal dt reference current is 0a. this optimal reference current may be achieved by either leaving the dt pin floating, or tying the dt pin to ground (gnd) with a 10m ? resistor. case 2: channels with greater 17db loss at 1.5625ghz: for channels exhibiting more than 25db of total loss (this includes cable or fr-4 loss) the dt pin should be configured for a refere nce sink current (coming out of the dt pin) of approximately 2a. a typical configuration for a 2a sink current is given in figure 27c. if the configuration in figure 27b is utilized, a 525k ? resistor is used. r21 r20 r1 t sdi t hdi t sck t hen di clk enb r1 r1 r1 r21 r21 r21 qlx4300-s45 (d) qlx4300-s45 (c) qlx4300-s45 (b) qlx4300-s45 (a) figure 26. timing diagram for programming multip le qlx4300-s45 devices using di/do carryover figure 27a. figure 27b. figure 27c. figure 27.
qlx4300-s45 fn6982 rev 1.00 page 18 of 21 november 19, 2009 typical application reference designs figures 28 and 29 show reference design schematics for a qlx4300-s45 evaluation board with an sma connector interface. figure 28 shows the schematic for the case when the equalizer boost level is set via the cp pins. figure 29 shows the schematic for the case when the level is set via the serial bus interface. figure 28. application circuit for the qlx4300-s4 5 evaluation board using the control pins for setting the equalizer compensation level 1 2 3 4 5 6 7 8 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 16 17 18 19 20 21 22 23 9 10 11 12 13 14 15 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 di do cp3[a] cp3[b] c p3[c] c p4[a] c p4[b] cp4[c] clk e nb cp1[a] c p1[b] cp1[ c] cp2[ a] cp2[b] c p2[c] gnd is2 is1 mode is4 is3 1.2v 1.2v 1.2v 1.2v 1.2v 1.2v dt in1[p] in1[n] in2[p] in2[n] in3[p] in3[n] in4[p] in4[n] out2[p] out2[n] out4[p] out4[n] out1[p] out1[n] out3[p] out3[n] 6ko bgref a qlx4300-s45 1.2v 100pf* 10nf bypass circuit for each v dd pin: 4, 7, 10, 29, 32, 35 (*100pf capacitor should be positioned closest to the pin) eq boost control for channels 1 and 2 (see pages 15-17) nc nc nc nc detection threshold reference current qlx4300-s45 lane extender reference control pin mode quellan, inc. eq boost control for channels 3 and 4 (see pages 15-17) = sma connector a) dc blocking capacitors = x7r or cog 0.1f (>4ghz bandwidth) impedance select (channels 3 and 4) impedance select (channels 1 and 2) mode mode at 1.2v: serial control mode mode at gnd: binary control mode 1.2v 100k 47nf 42.2k ?
qlx4300-s45 fn6982 rev 1.00 page 19 of 21 november 19, 2009 figure 29. application circuit for the qlx4300-s45 evaluation board using the serial bus interface for setting the eq ualizer compensation level typical application reference designs (continued) figures 28 and 29 show reference design schematics for a qlx4300-s45 evaluation board with an sma connector interface. figure 28 shows the schematic for the case when the equalizer boost level is set via the cp pins. figure 29 shows the schematic for the case when the level is set via the serial bus interface. 1 2 3 4 5 6 7 8 46 45 44 43 42 41 40 39 16 17 18 19 20 21 22 23 9 10 11 12 13 14 15 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 gnd is2 is1 mode is4 is3 1.2v 1.2v 1.2v 1.2v 1.2v 1.2v dt in1[p] in1[n] in2[p] in2[n] in3[p] in3[n] in4[p] in4[n] out2[p] out2[n] out4[p] out4[n] out1[p] out1[n] out3[p] out3[n] 6ko bgref a qlx4300-s45 1.2v 100pf* 10nf bypass circuit for each v dd pin: 4, 7, 10, 29, 32, 35 (*100pf capacitor should be positioned closest to the pin) detection threshold reference current qlx4300-s45 lane extender reference serial control mode quellan, inc. = sma connector a) dc blocking capacitors = x7r or cog 0.1f (>4ghz bandwidth) impedance select (channels 3 and 4) impedance select (channels 1 and 2) di d o cp3[a] c p3[b] cp3 [c] cp4 [a] cp4 [b] c p4[c] nc serial data in serial data out clk enb cp1[a] cp1[b] cp1[c] cp2[a] cp2[b] cp2[c] nc serial clock in enable active low mode at 1.2v: serial control mode mode at gnd: binary control mode 1.2v 100k 47nf 42.2k ?
fn6982 rev 1.00 page 20 of 21 november 19, 2009 qlx4300-s45 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas llc 2009. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. about q:active ? intersil has long realized that to enable the complex server clusters of next generation datacenters, it is critical to manage the signal integrity issues of electrical interconnects. to address this, intersil has developed its groundbreaking q:active ? product line. by integrating its analog ics inside cabling interconnects, intersil is able to achieve unsurpassed improvements in reach, power consumption, latency, and cable gauge size as well as increased airflow in tomorrow?s datacenters. this new technology transforms passive cabling into intelligent ?roadways? that yield lower operating expenses and capital expenditures for the expanding datacenter. intersil lane extenders allow greater reach over existing cabling while reducing the need for thicker cables. this significantly reduces cable weight and clutter, increases airflow, and reduces power consumption.
qlx4300-s45 fn6982 rev 1.00 page 21 of 21 november 19, 2009 package outline drawing l46.4x7 46 lead thin quad flat no-lead plastic package (tqfn) rev 0, 9/09 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but mus t be between 0.15mm and 0.30mm from the terminal tip. dimension applies to the metal lized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view c 0.152 ref 0 . 05 max. 0 . 00 min. 5 4.00 a b 7.00 (4x) 0.05 6 pin 1 index area 39 46 2.80 42x 0.40 exp. dap 15 1 38 23 46x 0.40 16 6 5.60 ( 6.80 ) ( 5.50 ) ( 46 x 0.60) (46x 0.20) ( 42x 0.40) ( 3.80 ) ( 2.50) 2.50 0.1 0.10 46x 0.20 a mc b 4 5.50 0.1 exp. dap 0.70 0.05 see detail "x" seating plane 0.05 0.10 c c c 24 side view pin 1 index area

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